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Project Planning
- Feasibility study and product definition
- Technology evaluation
- Cost evaluation
- Project scheduling
IC and IP blocks design
- Schematic design and entry
- Modeling / Simulation
- Layout design
- Physical verification
- JDV
- Test strategy development
Whole chip and blocks layout design
- Layout design
- Physical verification
- JDV (for chip)
Post-manufacture evaluation and characterization
- Manufacture coordination
- Bench evaluation
- Test program and test board development
- Test and characterization
PDK development
- Tech file development
- CDF development
- P-Cells development
- DRC command files development
- LVS command files development
Contact Us
E-mail: sales@luminten.com


